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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. AD7866 dual 1 msps, 12-bit, 2-channel sar adc with serial interface features dual 12-bit, 2-channel adc fast throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v low power 11.4 mw max at 1 msps with 3 v supplies 24 mw max at 1 msps with 5 v supplies wide input bandwidth 70 db snr at 300 khz input frequency on-board reference 2.5 v ?0 c to +125 c operation flexible power/throughput rate management simultaneous conversion/read no pipeline delays high speed serial interface spi tm /qspi tm / microwire tm /dsp compatible shutdown mode: 1 a max 20-lead tssop package functional block diagram v a2 v a1 dgnd d out a ref select v ref a0 12-bit successive approximation adc AD7866 2.5v ref t/h mux buf output drivers range sclk cs control logic v b2 v b1 d out b 12-bit successive approximation adc t/h mux output drivers buf d cap aav dd dv dd d cap b agnd agnd v drive general description the AD7866 is a dual 12-bit high speed, low power, successive approximation adc. the part operates from a single 2.7 v to 5.25 v power supply and features throughput rates up to 1 m sps. the device contains two adcs, each preceded by a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 10 mhz. the conversion process and data acquisition are controlled using standard control inputs, allowing easy interfacing to microprocessors or dsps. the input signal is sampled on the falling edge of cs ; conversion is also initiated at this point. the conversion time is determined by the sclk fre quency. there are no pipelined delays associated with the part. the AD7866 uses advanced design techniques to achieve very low power dissipation at high throughput rates. with 3 v supplies and 1 msps throughput rate, the part consumes a maximum of 3.8 ma. with 5 v supplies and 1 msps, the current consumption is a maximum of 4.8 ma. the part also offers flexible power/throughput rate management when operating in sleep mode. the analog input range for the part can be selected to be a 0 v to v ref range or a 2 v ref range with either straight binary or twos complement output coding. the AD7866 has an on-chip 2.5 v reference that can be overdriven if an external reference is preferred. each on-board adc can also be supplied with a separate individual external reference. the AD7866 is available in a 20-lead thin shrink small outline (tssop) package. product highlights 1. the AD7866 features two complete adc functions, allowing simultaneous sampling and conversion of two channels. each adc has a 2-channel input multiplexer. the conversion result of both channels is available simultaneously on separate data lines, or may be taken on one data line if only one serial port is available. 2. high throughput with low power consumption?he AD7866 offers a 1 msps throughput rate with 11.4 mw maximum power consumption when operating at 3 v. 3. flexible power/throughput rate management?he conver- sion rate is determined by the serial clock, allowing the power consumption to be reduced as the conversion time is reduced through a sclk frequency increase. power efficiency can be maximized at lower throughput rates if the part enters sleep during conversions. 4. no pipeline delay?he part features two standard successive approximation adcs with accurate control of the sampling instant via a cs input and once off conversion control.
rev. a ? AD7866?pecifications (t a = t min to t max , v dd = 2.7 v to 5.25 v, v drive = 2.7 v to 5.25 v, reference = 2.5 v external on d cap a and d cap b, f sclk = 20 mhz, unless otherwise noted.) parameter a version 1 b version 1 unit test conditions/comments dynamic performance signal to noise + distortion (sinad) 2 68 68 db min f in = 300 khz sine wave, f s = 1 msps total harmonic distortion (thd) 2 ?5 ?5 db max f in = 300 khz sine wave, f s = 1 msps peak harmonic or spurious noise (sfdr) 2 ?6 ?6 db max f in = 300 khz sine wave, f s = 1 msps intermodulation distortion (imd) 2 second order terms ?8 ?8 db typ third order terms ?8 ?8 db typ channel-to-channel isolation ?8 ?8 db typ sample and hold aperture delay 3 10 10 ns max aperture jitter 3 50 50 ps typ aperture delay matching 3 200 200 ps max full power bandwidth 12 12 mhz typ @ 3 db 22 mhz typ @ 0.1 db dc accuracy resolution 12 12 bits integral nonlinearity 1.5 1 lsb max b g rade, 0 v to v ref range only; 0.5 lsb typ 1.5 lsb max 0 v to 2 v ref range; 0.5 lsb typ differential nonlinearity ?.95/+1.25 ?.95/+1.25 lsb max guaranteed no missed codes to 12 bits 0 v to v ref input range straight binary output coding offset error 8 8 lsb max offset error match 1.2 1.2 lsb typ gain error 2.5 2.5 lsb max gain error match 0.2 0.2 lsb typ 2 v ref input range ? ref to +v ref biased about v ref with positive gain error 2.5 2.5 lsb max twos complement output coding zero code error 8 8 lsb max zero code error match 0.2 0.2 lsb typ negative gain error 2.5 2.5 lsb max analog input input voltage ranges 0 to v ref 0 to v ref v range pin low upon cs falling edge 0 to 2 v ref 0 to 2 v ref v range pin high upon cs falling edge dc leakage current 500 500 na max t a = ?0 c to +85 c 11 a max 85 c < t a 125 c input capacitance 30 30 pf typ when in track 10 10 pf typ when in hold reference input/output reference input voltage 2.5 2.5 v 1% for specified performance reference input voltage range 4 2/3 2/3 v min/v max ref select pin tied high dc leakage current 30 30 a max v ref pin 160 160 a max d cap a, d cap b pins input capacitance 20 20 pf typ reference output voltage 5 2.45/2.55 2.45/2.55 v min/v max v ref output impedance 6 25 25 ? typ v dd = 5 v 45 45 ? typ v dd = 3 v reference temperature coefficient 50 50 ppm/ c typ ref out error (t min to t max ) 15 15 mv typ logic inputs input high voltage, v inh 0.7 v drive 0.7 v drive v min input low voltage, v inl 0.3 v drive 0.3 v drive v max input current, i in 1 1 a max typically 15 na, v in = 0 v or v drive input capacitance, c in 3 10 10 pf max logic outputs output high voltage, v oh v drive ?0.2 v drive ?0.2 v min i source = 200 a output low voltage, v ol 0.4 0.4 v max i sink = 200 a floating-state leakage current 1 1 a max v dd = 2.7 v to 5.25 v floating-state output capacitance 3 10 10 pf max output coding straight (natural) binary selectable with either input range twos complement
rev. a AD7866 ? parameter a version 1 b version 1 unit test conditions/comments conversion rate conversion time 16 16 sclk cycles 800 ns with sclk = 20 mhz track/hold acquisition time 3 300 300 ns max throughput rate 1 1 msps max see serial interface section power requirements v dd 2.7/5.25 2.7/5.25 v min/max v drive 2.7/5.25 2.7/5.25 v min/max i dd 7 digital i/ps = 0 v or v drive normal mode (static) 3.1 3.1 ma max v dd = 4.75 v to 5.25 v. add 0.5 ma typical if using internal reference. 2.8 2.8 ma max v dd = 2.7 v to 3.6 v. add 0.35 ma typical if using internal reference. operational, f s = 1 msps 4.8 4.8 ma max v dd = 4.75 v to 5.25 v. add 0.5 ma typical if using internal reference. 3.8 3.8 ma max v dd = 2.7 v to 3.6 v. add 0.5 ma typical if using internal reference. partial power-down mode 1.6 1.6 ma max f s = 100 ksps, f sclk = 20 mhz add 0.2 ma typ if using internal reference. partial power-down mode 560 560 a max (static) add 100 a typical if using internal reference. full power-down mode 1 1 a max sclk on or off. t a = ?0 c to +85 c 22 a max sclk on or off. 85 c < t a 125 c power dissipation 7 normal mode (operational) 24 24 mw max v dd = 5 v 11.4 11.4 mw max v dd = 3 v partial power-down (static) 2.8 2.8 mw max v dd = 5 v. sclk on or off. 1.68 1.68 mw max v dd = 3 v. sclk on or off. full power-down (static) 5 5 w max v dd = 5 v. sclk on or off. 33 w max v dd = 3 v. sclk on or off. notes 1 temperature ranges as follows: a, b versions: ?0 c to +125 c. 2 see terminology section. 3 sample tested @ 25 c to ensure compliance. 4 external reference range that may be applied at v ref , d cap a, or d cap b. 5 relates to pins v ref , d cap a, or d cap b. 6 see reference section for d cap a, d cap b output impedances. 7 see power vs. throughput rate section. specifications subject to change without notice.
rev. a ? AD7866 timing specifications 1 (v dd = 2.7 v to 5.25 v, v drive = 2.7 v to 5.25 v, v ref = 2.5 v; t a = t min to t max , unless otherwise noted.) limit at parameter t min , t max unit description f sclk 2 10 khz min 20 mhz max t convert 16 t sclk ns max t sclk = 1/f sclk 800 ns max f sclk = 20 mhz t quiet 50 ns max minimum time between end of serial read and next falling edge of cs t 2 10 ns min cs to sclk setup time t 3 3 25 ns max delay from cs until d out a and d out b three-state disabled t 4 3 40 ns max data access time after sclk falling edge. v drive 3 v, c l = 50 pf; v drive < 3 v, c l = 25 pf t 5 0.4 t sclk ns min sclk low pulsewidth t 6 0.4 t sclk ns min sclk high pulsewidth t 7 10 ns min sclk to data valid hold time t 8 4 25 ns max cs rising edge to d out a, d out b, high impedance t 9 4 10 ns min sclk falling edge to d out a, d out b, high impedance 50 ns max sclk falling edge to d out a, d out b, high impedance notes 1 sample tested at 25 c to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. 2 mark/space ratio for the clk input is 40/60 to 60/40. 3 measured with the load circuit of figure 1 and defined as the time required for the output to cross 0.8 v or 2.0 v. 4 t 8, t 9 are derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 1. the mea sured number is then extrapo- lated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times t 8 and t 9 quoted in the timing characteristics are the true bus relinquish times of the part and are independent of the bus loading. specifications subject to change without notice. 1.6v 200 ai ol 200 a i oh c l 50pf to output pin figure 1. load circuit for digital output timing specifications
rev. a AD7866 ? ordering guide resolution package model temperature range (bits) package description option AD7866aru ?0 c to +125 c1 2t hin shrink soc (tssop) ru-20 AD7866bru ?0 c to +125 c1 2t hin shrink soc (tssop) ru-20 eval-AD7866cb 1 evaluation board eval-control brd2 2 controller board notes 1 this can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonst ration purposes. 2 this evaluation board controller is a complete unit, allowing a pc to control and communicate with all analog devices evaluatio n boards ending in t he cb de sig n ators. to order a complete evaluation kit, the particular adc evaluation board, e.g., eval-AD7866cb, the eval-control brd2, and a 12 v transformer must be ordered. see relevant evaluation board technical note for more information. absolute maximum ratings 1 (t a = 25 o c, unless otherwise noted.) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v drive to dgnd . . . . . . . . . . . . . . . . ?.3 v to dv dd + 0.3 v v drive to agnd . . . . . . . . . . . . . . . . ?.3 v to av dd + 0.3 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v analog input voltage to agnd . . . . . ?.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . . . . . . . . . ?.3 v to +7 v v ref to agnd . . . . . . . . . . . . . . . . . . ?.3 v to av dd + 0.3 v digital output voltage to dgnd . . . ?.3 v to v drive + 0.3 v input current to any pin except supplies 2 . . . . . . . . . 10 ma operating temperature range commercial (a, b versions) . . . . . . . . . . . . . ?0 c to +125 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c tssop package, power dissipation . . . . . . . . . . . . . 450 mw ja thermal impedance (tssop) . . . . . . . . . . . . . 143 c/w jc thermal impedance (tssop) . . . . . . . . . . . . . . 45 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kv notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7866 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a ? AD7866 pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD7866 ref select a0 d cap b agnd v b2 v b1 v a2 v a1 agnd d cap a v ref cs sclk v drive d out b d out a dgnd dv dd av dd range pin function descriptions pin no. mnemonic function 1 ref select internal/external reference selection. logic input. if this pin is tied to gnd, the on-chip 2.5 v reference is used as the reference source for both adc a and adc b. in addition, pins v ref , d cap a, and d cap b must be tied to decoupling capacitors. if the ref select pin is tied to a logic high, an external refer- ence can be supplied to the AD7866 through the v ref pin, in which case decoupling capacitors are required on d cap a and d cap b. however, if the v ref pin is tied to agnd while ref select is tied to a logic low, an individual external reference can be applied to both adc a and adc b through pins d cap a and d cap b, respectively. see the reference configuration options section. 2, 9 d cap b, d cap a decoupling capacitors are connected to these pins to decouple the reference buffer for each respective adc. the on-chip reference can be taken from these pins and applied externally to the rest of a system. depending on the polarity of the ref select pin and the configuration of the v ref pin, these pins can also be used to input a separate external reference to each adc. the range of the external reference is dependent on the analog input range selected. see the reference configuration options section. 3, 8 agnd analog ground. ground reference point for all analog circuitry on the AD7866. all analog input signals and any external reference signal should be referred to this agnd voltage. both of these pins should connect to the agnd plane of a system. the agnd and dgnd voltages ideally should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 4, 5 v b2 , v b1 analog inputs of adc b. single-ended analog input channels. the input range on each channel is 0 v to v ref or a 2 v ref range depending on the polarity of the range pin upon the falling edge of cs . 6, 7 v a2 , v a1 analog inputs of adc a. single-ended analog input channels. the input range on each channel is 0 v to v ref or a 2 v ref range depending on the polarity of the range pin upon the falling edge of cs . 10 v ref reference decoupling and external reference selection. this pin is connected to the internal reference and requires a decoupling capacitor. the nominal reference voltage is 2.5 v, which appears at the pin; however, if the internal reference is to be used externally in a system, it must be taken from either the d cap a or d cap b pins. this pin is also used in conjunction with the ref select pin when applying an external ref erence to the AD7866. see the ref select pin description.
rev. a AD7866 ? pin function descriptions (continued) pin no. mnemonic function 11 range analog input range and output coding selection. logic input. the polarity on this pin will determine what input range the analog input channels on the AD7866 will have, and will also select the type of output coding the adc will use for the conversion result. on the falling edge of cs , the polarity of this pin is checked to determine the analog input range of the next conversion. if this pin is tied to a logic low, the analog input range is 0 v to v ref and the output coding from the part will be straight binary (for the next conversion). if this pin is tied to a logic high when cs goes low, the analog input range is 2 v ref and the output coding for the part will be twos complement. how- ever, if after the falling edge of cs the logic level of the range pin has changed upon the eighth sclk falling edge, the output coding will change to the other option without any change in the analog input range. (see the analog input and adc transfer function sections.) 12 av dd analog supply voltage, 2.7 v to 5.25 v. this is the only supply voltage for all analog circuitry on the AD7866. the av dd and dv dd voltages ideally should be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to agnd. 13 dv dd digital supply voltage, 2.7 v to 5.25 v. this is the supply voltage for all digital circuitry on the AD7866. the dv dd and av dd voltages should ideally be at the same potential and must not be more than 0.3 v apart even on a transient basis. this supply should be decoupled to dgnd. 14 dgnd digital ground. this is the ground reference point for all digital circuitry on the AD7866. the dgnd and agnd voltages ideally should be at the same potential and must not be more than 0.3 v apart even on a transient basis. 15, 16 d out a, d out b serial data outputs. the data output is supplied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data appears on both pins simultaneously from the simultaneous conversions of both adcs. the data stream consists of one leading zero followed by three status bits, followed by the 12 bits of conversion data. the data is provided msb first. if cs is held low for another 16 sclk cycles after the conversion data has been output on either d out a or d out b, the data from the other adc follows on the d out pin. this allows data from a simultaneous conversion on both adcs to be gathered in serial format on either d out a or d out b alone using only one serial port. see the serial interface section. 17 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the interface will operate. this pin should be decoupled to dgnd. 18 sclk serial clock. logic input. a serial clock input provides the sclk for accessing the data from the AD7866. this clock is also used as the clock source for the conversion process. 19 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the AD7866 and frames the serial data transfer. 20 a0 multiplexer select. logic input. this input is used to select the pair of channels to be converted simultaneously, i.e., channel 1 of both adc a and adc b, or channel 2 of both adc a and adc b. the logic state of this pin is checked upon the falling edge of cs, and the multiplexer is set up for the next conversion. if it is low, the following conversion will be performed on channel 1 of each adc; if it is high, the following conversion will be performed on channel 2 of each adc.
rev. a ? AD7866 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end points of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this applies to straight binary output coding. it is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 1 lsb. offset error match this is the difference in offset error between the two channels. gain error this applies to straight binary output coding. it is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., v ref ?1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between the two channels. zero code error this applies when using the twos complement output coding option, in particular with the 2 v ref input range as ? ref to +v ref biased about the v ref point. it is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, i.e., v ref ?1 lsb. zero code error match this refers to the difference in zero code error between the two channels. positive gain error this applies when using the twos complement output coding option, in particular with the 2 v ref input range as ? ref to +v ref biased about the v ref point. it is the deviation of the last code transition (011 . . . 110) to (011 . . . 111) from the ideal (i.e., +v ref ?1 lsb) after the zero code error has been adjusted out. negative gain error this applies when using the twos complement output coding option, in particular with the 2 v ref input range as ? ref to +v ref biased about the v ref point. it is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e., ? ref + 1 lsb) after the zero code error has been adjusted out. track-and-hold acquisition time the track-and-hold amplifier returns into track mode after the end of conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal-to-(noise + distortion) ratio (sndr) this is the measured ratio of signal-to-(noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to- ( noise + distortion ) = (6.02 n + 1.76) db thus, for a 12-bit converter, this is 74 db. total harmonic distortion (thd) total harmonic distortion is the ratio of the rms sum of har- monics to the fundamental. for the AD7866, it is defined as: thd db vv vvv v () = ++++ 20 2 2 3 2 4 2 5 2 6 2 1 log where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum. but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion prod ucts at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa ?fb), while the third order terms include (2fa + fb), (2fa ?fb), (fa + 2fb), and (fa ?2fb). the AD7866 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified sepa- rately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in db. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full-scale (2 v ref ), 455 khz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 10 khz signal (0 v to v ref ). the figure given is the worst-case across all four channels for the AD7866. psr (power supply rejection) see the performance curves section.
rev. a AD7866 ? t ypical performance characteristics frequency ?khz 0 ?5 ?15 0 500 100 snr ?db 200 300 400 ?5 ?5 ?5 50 150 250 350 450 4098 point fft f sample = 1msps f in = 300khz snr = 70.31db thd = ?5.47db sfdr = ?6.64db ?5 tpc 1. dynamic performance input frequency ?hz ?1 ?5 10k 1m 100k sinad ?db ?3 ?3 ?7 ?9 ?1 ?5 t a = 25 c v dd = v drive = 2.7v v dd = v drive = 3.6v v dd = v drive = 5.25v v dd = v drive = 4.75v tpc 2. sinad vs. input frequency av dd ripple frequency ?hz 0 ?00 1k psrr ?db 10k ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100k 1m 100mv p-p sine wave on av dd 2.5v ext reference on v ref t a = 25 c v dd = 2.7v v dd = 5.25v v dd = 4.75v v dd = 3.6v tpc 3a. psrr vs. supply ripple frequency, without supply decoupling av dd ripple frequency ?hz 0 ?00 1k psrr ?db 10k ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100k 1m 100mv p-p sine wave on av dd 2.5v ext reference on d cap a, d cap b t a = 25 c v dd = 2.7v v dd = 5.25v v dd = 4.75v v dd = 3.6v tpc 3b. psrr vs. supply ripple frequency, without supply decoupling performance curves tpc 1 shows a typical fft plot for the AD7866 at 1 mhz sample rate and 300 khz input frequency. tpc 2 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 msps with an sclk of 20 mhz. tpcs 3a to 4b show the power supply rejection ratio versus av dd supply ripple frequency for the AD7866 under different conditions. the power supply rejection ratio (psrr) is defined as the ratio of the power in the adc output at full-scale fre- quency f, to the power of a 100 mv sine wave applied to the adc av dd supply of frequency f s : psrr db pf pf s () = () 10 log pf = power at frequency f in adc output, and pf s = power at frequency f s coupled onto the adc av dd supply. here, a 100 mv peak-to-peak sine wave is coupled onto the av dd supply while the digital supply is left unaltered. tpcs 3a and 3b show the psrr of the AD7866 when there is no decoupling on the supply, while tpcs 4a and 4b show the psrr with decoupling capacitors of 10 f and 0.1 f on the supply. tpcs 5 and 6 show typical dnl and inl plots for the AD7866. tpc 7 shows a graph of the total harmonic distortion versus analog input frequency for various source impedances. tpc 8 shows a graph of total harmonic distortion versus analog input frequency for various supply voltages. see the analog input section.
rev. a ?0 AD7866 av dd ripple frequency ?hz 0 ?00 1k psrr ?db 10k ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100k 1m 100mv p-p sine wave on av dd 2.5v ext reference on v ref t a = 25 c v dd = 2.7v v dd = 3.6v tpc 4a. psrr vs. supply ripple frequency, with supply decoupling av dd ripple frequency ?hz 0 ?00 1k psrr ?db 10k ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100k 1m 100mv p-p sine wave on av dd 2.5v ext reference on d cap a, d cap b t a = 25 c v dd = 2.7v v dd = 4.75v v dd = 3.6v tpc 4b. psrr vs. supply ripple frequency, with supply decoupling adc ?code 1.0 0 dnl ?lsb 0.8 0.6 0.4 0.2 0 ?.2 ?.4 ?.6 ?.8 ?.0 500 1000 1500 2000 2500 3000 3500 4000 tpc 5. dc dnl plot adc ?code 1.0 0 inl ?lsb 0.0 0.8 0.6 0.4 0.2 ?.2 ?.4 ?.6 ?.8 ?.0 500 1000 1500 2000 2500 3000 3500 4000 tpc 6. dc inl plot input frequency ?hz ?0 10k thd ?db ?5 ?0 ?5 ?0 ?5 ?0 100k 1000k t a = 25 c v dd = 4.75v r in = 100 r in = 50 r in = 10 tpc 7. thd vs. analog input frequency for various source impedances input frequency ?hz ?0 10k thd ?db ?2 ?4 ?6 ?8 ?0 ?2 100k 1000k t a = 25 c ?4 ?6 ?8 ?0 v dd = v drive = 2.7v v dd = v drive = 3.6v v dd = v drive = 4.75v v dd = v drive = 5.25v tpc 8. thd vs. analog input frequency for various supply voltages
rev. a AD7866 ?1 circuit information the AD7866 is a fast, micropower, dual 12-bit, single supply, a/d converter that operates from a 2.7 v to 5.25 v supply. when operated from either a 5 v supply or a 3 v supply, the AD7866 is capable of throughput rates of 1 msps when pro vided with a 20 mhz clock. the AD7866 contains two on-chip track-and-hold amplifiers, two successive approximation a/d converters, and a serial inter- face with two separate data output pins, and is housed in a 20-lead tssop package, which offers the user considerable space-saving advan tages over alternative solutions. the serial clock input accesses data from the part but also provides the clock source for each successive approximation adc. the ana- log input range for the part can be selected to be a 0 v to v ref input or a 2 v ref input with either straight binary or twos complement output coding. the AD7866 has an on-chip 2.5 v reference that can be overdriven if an external reference is pre- ferred. in addition, each adc can be supplied with an individual separate external refer ence. the AD7866 also features power-down options to allow power saving between conversions. the power-down feature is imple- mented across the standard serial interface, as described in the modes of operation section. converter operation the AD7866 has two successive approximation analog-to- digital converters, each based around a capacitive dac. figures 2 and 3 show simplified schematics of one of these adcs. the adc is comprised of control logic, a sar, and a capacitive dac, all of which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. figure 2 shows the adc during its acquisi tion phase. sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on v a1 , for example. capacitive dac control logic comparator sw2 sw1 a b agnd v in figure 2. adc acquisition phase when the adc starts a conversion (see figure 3), sw2 will open and sw1 will move to position b, causing the comparator to become unbalanced. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figures 10 and 11 show the adc transfer functions. capacitive dac control logic comparator sw2 sw1 a b agnd v in figure 3. adc conversion phase analog input figure 4 shows an equivalent circuit of the analog input struc ture of the AD7866. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mv. this will cause these diodes to become forward- biased and start conducting current into the substrate. 10 ma is the maximum current these diodes can conduct without causing irreversible damage to the part. the capacitor c1 in figure 4 is typically about 10 pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of a switch. this resistor is typically about 100 ? . the capacitor c2 is the adc sampling capacitor and has a capacitance of 20 pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc low-pass filter on the relevant analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a function of the particular application. v dd v in c1 d1 d2 r1 convert phase ?switch open track phase ?switch closed c2 figure 4. equivalent analog input circuit when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases, and performance will degrade (see tpc 7).
rev. a ?2 AD7866 analog input ranges the analog input range for the AD7866 can be selected to be 0 v to v ref or 2 v ref with either straight binary or twos complement output coding. the range pin is used to select both the analog input range and the output coding, as shown in figures 5 to 8. on the falling edge of cs , point a, the logic level of the range pin is checked to determine the analog input range of the next conversion. if this pin is tied to a logic low, the analog input range will be 0 v to v ref and the output coding from the part will be straight binary (for the next conversion). if this pin is at a l ogic high when cs goes low, the analog input range will be 2 v ref and the output coding for the part will be twos complement. how- ever, if after the falling edge of cs , the logic level of the range pin has changed upon the eighth falling sclk edge, point b, the output coding will change to the other option without any change in the analog input range. so for the next conversion, twos complement output coding could be selected with a 0 v to v ref input range, for example, if the range pin is low upon the falling edge of cs and high upon the eighth falling sclk edge, as shown in figure 7. figures 5 to 8 show examples of timing diagrams for selections of different analog input ranges with various output coding formats. table i summarizes the required logic level of the range pin for each selection. note that the analog input range selected must not exceed v dd . the logic input a0 is used to select the pair of channels to be con verted simultaneously. the logic state of this pin is also checked upon the falling edge of cs , and the multiplexers are set up for the next conversion. if it is low, the following conversion will be per formed on channel 1 of each adc; if it is high, the following conversion will be performed on channel 2 of each adc. handling bipolar input signals figure 9 shows how useful the combination of the 2 v ref input range and the twos complement output coding scheme is for handling bipolar input signals. if the bipolar input signal is biased about v ref and twos complement output coding is selected, then v ref becomes the zero code point, ? ref is negative full-scale, and +v ref becomes positive full-scale with a dynamic range of 2 v ref . transfer functions the designed code transitions occur at successive integer lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size is v ref /4096. the ideal transfer characteristic for the AD7866 when straight binary coding is selected is shown in figure 10, and the ideal transfer characteristic for the AD7866 when twos complement coding is selected is shown in figure 11. table i. analog input and output coding selection range level range level @ point a 1 @ point b 2 input range 3 output coding 3 low low 0 v to v ref straight binary high high v ref v ref twos complement low high v ref /2 v ref /2 twos complement high low 0 v to 2 v ref straight binary notes 1 point a = falling edge of cs. 2 point b = eighth falling edge of sclk. 3 selected for next conversion. straight binary 0v to v ref input range cs sclk range d out a d out b 1816 16 1 ab figure 5. selecting 0 v to v ref input range with straight binary output coding cs sclk range d out a d out b 1816 16 1 ab v ref v ref input range twos complement figure 6. selecting v ref v ref input range with twos complement output coding
rev. a AD7866 ?3 cs sclk range d out a d out b 1816 16 1 ab v ref /2 v ref /2 input range twos complement figure 7. selecting v ref /2 v ref /2 input range with twos complement output coding cs sclk range d out a d out b 1816 16 1 ab 0v to 2 v ref input range straight binary figure 8. selecting 0 v to 2 v ref input range with straight binary output coding ref select v ref AD7866 d out d cap a d cap b v drive v in 470nf 470nf 100nf v ref r4 r3 r2 v r1 v 0v twos complement 011 111 +v ref v ref ? ref (= 2 v ref ) 000 000 100 000 (= 0v) r1 = r2 = r3 = r4 v dd v dd dsp/ p figure 9. handling bipolar signals with the AD7866 000...000 0v analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb v ref ?1lsb 1lsb = v ref /4096 adc code figure 10. straight binary transfer characteristic with 0 v to v ref input range 100...000 analog input 011...110 100...001 100...010 000...001 111...111 1lsb = 2 v ref /4096 adc code 011...111 000...000 +v ref ?1lsb ? ref + 1lsb v ref ?1lsb figure 11. twos complement transfer characteristic with v ref v ref input range
rev. a ?4 AD7866 digital inputs the digital inputs applied to the AD7866 are not limited by the maximum ratings that limit the analog inputs. instead, the digital inputs applied can go to 7 v and are not restricted by the v dd + 0.3 v limit as on the analog inputs. see maximum ratings. another advantage of sclk, range, ref select, a0, and cs not being restricted by the v dd + 0.3 v limit is that power supply sequencing issues are avoided. if one of these digital inputs is applied before v dd , there is no risk of latch-up, as there would be on the analog inputs if a signal greater than 0.3 v were applied prior to v dd . v drive the AD7866 also has the v drive feature, which controls the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the AD7866 was operated with a v dd of 5 v, the v drive pin could be powered from a 3 v supply, allowing a large dynamic range with low voltage digital processors. for example, the AD7866 could be used with the 2 v ref input range, with a v dd of 5 v while still being able to interface to 3 v digital parts. reference configuration options the AD7866 has various reference configuration options. the ref select pin allows the choice of using an internal 2.5 v reference or applying an external reference, or even an indi vidual external reference for each on-chip adc if desired. if the ref select pin is tied to agnd, then the on-chip 2.5 v refer ence is used as the reference source for both adc a and adc b. in addition, pins v ref , d cap a, and d cap b must be tied to decoupling capacitors (100 nf, 470 nf, and 470 nf recommended, respectively). if the ref select pin is tied to a logic high, an external reference can be supplied to the AD7866 through the v ref pin to overdrive the on-chip reference, in which case decoupling capacitors are required on d cap a and d cap b again. however, if the v ref pin is tied to agnd while ref select is tied to a logic low, an individual external reference can be applied to both adc a and adc b through pins d cap a and d cap b, respectively. table ii summarizes these reference op tions. for specified performance, the last configuration was used with the same reference voltage applied to both d cap a and d cap b. the connections for the relevant reference pins are shown in the typical connection diagrams. if the internal reference is being used, the v ref pin should have a 100 nf capacitor connected to agnd very close to the v ref pin. these connections are shown in figure 12. d cap b d cap a v ref 470nf AD7866 470nf 100nf figure 12. relevant connections when using an internal reference d cap b d cap a v ref AD7866 v ref ref select figure 13. relevant connections when applying an external reference at d cap a and/or d cap b d cap b d cap a v ref 470nf AD7866 470nf v ref ref select v drive figure 14. relevant connections when applying an external reference at v ref figure 13 shows the connections required when an external reference is applied to d cap a and d cap b. in this example, the same reference voltage is applied at each pin; however, a different voltage may be applied at each of these pins for each on-chip adc. an external reference applied at these pins may have a range from 2 v to 3 v, but for specified performance it must be within 1% of 2.5 v. figure 14 shows the third option, which is to overdrive the internal reference through the v ref pin. this is possible due to the series resistance from the v ref pin to the internal reference. this external reference can have a range from 2 v to 3 v; but again, to get as close as possible to the specified performance, a 2.5 v reference is desirable. d cap a and d cap b decouple each on-chip reference buffer, as shown in figure 15. table ii. reference selection reference option ref select v ref 1 d cap a and d cap b 2 internal low decoupling capacitor decoupling capacitor externally through v ref high external reference decoupling capacitor externally through d cap a and/or d cap b low agnd external reference a and/or reference b notes 1 recommended value of decoupling capacitor = 100 nf. 2 recommended value of decoupling capacitor = 470 nf.
rev. a AD7866 ?5 100nf 2.5v ref adc b ext ref ext ref 470nf d cap b d cap a v ref ext ref 470nf buf b adc a buf a figure 15. reference circuit if the on-chip 2.5 v reference is being used, and is to be applied externally to the rest of the system, it may be taken from either the v ref pin or one of the d cap a or d cap b pins. if it is taken from the v ref pin, it must be buffered before being applied elsewhere as it will not be capable of sourcing more than a few microamps. if the reference voltage is taken from either the d cap a pin or d cap b pin, a buffer is not strictly necessary. either pin is capable of sourcing current in the region of 100 a; how- ever, the larger the source current requirement, the greater the voltage drop seen at the pin. the output impedance of each of these pins is typically 50 ? . in addition, this point represents the actual voltage applied to the adc internally so any voltage drop due to the current load or disturbance due to a dynamic load will directly affect the adc conversion. for this reason, if a large current source is necessary or a dynamic load is present, it is recommended to use a buffer on the output to drive a device. examples of suitable external reference devices that may be ap- plied at pins v ref , d cap a, or d cap b are the ad780, ref192, ref43, and ad1582. modes of operation the mode of operation of the AD7866 is selected by controlling the (logic) state of the cs signal during a conversion. there are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. the point at which cs is pulled high after the conversion has been initiated will determine which power-down mode, if any, the device will enter. similarly, if already in a power-down mode, cs can con trol whether the device will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. normal mode this mode is intended for fastest throughput rate performance since the user does not have to worry about any power-up times with the AD7866 remaining fully powered all the time. figure 16 shows the general diagram of the operation of the AD7866 in this mode. the conversion is initiated on the falling edge of cs , as described in the serial interface section. to ensure that the part remains fully powered up at all times, cs must remain low until at least 10 sclk falling edges have elapsed after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge, but before the 16th sclk falling edge, the part will remain powered up but the conversion will be terminated and d out a and d out b will go back into three-state. sixteen serial clock cycles are required to complete the conversion and access the conversion result. the d out line will not return to three-state after 16 sclk cycles have elapsed, but instead when cs is brought high again. if cs is left low for another 16 sclk cycles, the result from the other adc on board will also be ac cessed on the same d out line, as shown in figure 22 (see also the serial inter face section). the status bits provided prior to each conversion result will identify which adc the following result will be from. once 32 sclk cycles have elapsed, the d out line will return to three-state on the 32nd sclk falling edge. if cs is brought high prior to this, the d out line will return to three-state at that point. thus, cs may idle low after 32 sclk cycles, until it is brought high again sometime prior to the next conversion (effectively idling cs low), if so desired, since the bus will still return to three-state upon completion of the dual result read. once a data transfer is complete and d out a and d out b have returned to three-state, another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. partial power-down mode this mode is intended for use in applications where slower throughput rates are required. either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the adc is then pow ered down for a relatively long duration between these bursts of several conversions. when the AD7866 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffer. to enter partial power-down, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the tenth falling edge of sclk as shown in figure 17. once cs has been brought high in this window of sclks, the part will enter partial power-down, the conversion that was initiated by the falling edge of cs will be sclk d out a d out b cs status bits and conversion result 1 16 10 figure 16. normal mode operation
rev. a ?6 AD7866 terminated, and d out a and d out b will go back into three- state. if cs is brought high before the second sclk falling edge, the part will remain in normal mode and will not power down. this will avoid accidental power-down due to glitches on the cs line. to exit this mode of operation and power up the AD7866 again, a dummy conversion is performed. on the falling edge of cs , the device will begin to power up, and will continue to power up as long as cs is held low until after the falling edge of the tenth sclk. in the case of an external reference, the device will be fully powered up once 16 sclks have elapsed, and valid data will result from the next conversion, as shown in figure 18. if cs is brought high before the second falling edge of sclk, the AD7866 will again go into partial power-down. this avoids accidental power-up due to glitches on the cs line; although the device may begin to power up on the falling edge of cs , it will power down again on the rising edge of cs . if the AD7866 is already in partial power-down mode and cs is brought high between the second and tenth falling edges of sclk, the device will enter full power-down mode. for more information on the power-up times associated with partial power-down in various configurations, see the power-up times section. full power-down mode this mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, as power-up from a full power-down takes substan tially longer than that from partial power-down. this mode is more suited to applications where a series of conversions performed at a rela- tively high throughput rate would be followed by a long period of inactivity and thus power-down. when the AD7866 is in full power-down, all analog circuitry is powered down. full power- down is entered in a similar way as partial power-dow n, except the timing sequence shown in figure 17 must be ex ecuted twice. the conversion process must be interrupted in a similar fashion by bringing cs high anywhere after the second falling edge of sclk and before the tenth falling edge of sclk. the device will enter partial power-down at this point. to reach full power-down, the next conversion cycle must be interrupted in the same way, as shown in figure 19. once cs has been brought high in this window of sclks, the part will power down completely. note that it is not necessary to complete the 16 sclks once cs has been brought high to enter a power-down mode. to exit full power-down and power the AD7866 up again, a dummy conversion is performed, as when powering up from partial power-down. on the falling edge of cs , the device will begin to power up and will continue to power up as long as cs is held low until after the falling edge of the tenth sclk. the power-up time required must elapse before a conversion can be initiated, as shown in figure 20. see the power-up times sec- tion for the power-up times associated with the AD7866. power-up times the AD7866 has two power-down modes, partial power-down and full power-down, which are described in detail in the m odes of operation section. this section deals with the power-up time required when coming out of either of these modes. it should be noted that the power-up times quoted apply with the recomm ended capacitors on the v ref , d cap a, and d cap b pins in place. to power up from full power- down, approximately 4 ms should be allowed from the falling edge of cs , shown in figure 20 as t power up . powering up from partial power-down requires much less time. if the internal reference is being used, the power-up time is typically 4 s; but if an external reference is being used, the power-up time is typically 1 s. this means that with any frequency of sclk up to 20 mhz, one dummy cycle w ill always be sufficient to allow the device to power up from p artial power- down when using an external reference (see figure 18). once the dummy cycle is complete, the adc will be fully pow ered up and the input signal will be acquired properly. a dummy cycle may well be sufficient to power up the part when using an internal reference also, provided the sclk is slow enough to allow the required power-up time to elapse before a valid conversion is requested. in addition, it should be ensured that the quiet time, t quiet , has still been allowed from the point where the bu s goes back into three-state after the dummy conversion to the next falling edge of cs . alternatively, instead of slowing the sclk to make the dummy cycle long enough, the cs high time could ju st be extended to include the required power-up time (as in figure 20) when powering up from full power-down. different power-up time is needed when coming out of partial power-down for two cases where an internal or external refer- ence is being used, primarily because of the on-chip reference buffers. they power down in partial power-d own mode and must be powered up again if the internal reference is being used, but they do not need to be powered up again if an external reference is being used. the time needed to power up these buffers is not just their own power-up time but also the time re qu ir ed to charge up the decoupling capacitors present on pins v ref , d cap a, and d cap b. it should also be noted that during power-up from partial power-down, the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 18. when power supplies are first applied to the AD7866, the adc may power up in either of the power-down modes or the normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. likewise, if the part is to be kept in the partial power-down mode immediately after the supplies are applied, two dummy cycles must be initiated. the first dummy cycle must hold cs low until after the tenth sclk falling edge (see figure 16); in the second cycle, cs must be brought high before the tenth sclk edge but after the second sclk falling edge (see figure 17). alternatively, if the part is to be placed in full power-down mode when the supplies have been applied, three dummy cycles must be initiated. the first dummy cycle must hold cs low until after the ten th sclk falling edge (see figure 16); the sec- ond and third dummy cycles place the part in full power-down (see figure 19). see also the modes of operation section. once supplies are applied to the AD7866, enough time must be allowed for any external reference to power up and charge any reference capacitor to its final value, or enough time must be allowed for the internal reference buffer to charge the various reference buffer decoupling capacitors to their final values.
rev. a AD7866 ?7 cs 1 16 10 2 three-state sclk d out a d out b figure 17. entering partial power-down mode 1 16 10 116 invalid data valid data cs sclk d out a d out b the part begins to power up the part may be fully powered up; see power-up times section a figure 18. exiting partial power-down mode 116 10 116 invalid data invalid data three-state three-state 2 2 10 cs sclk d out a d out b the part enters partial power-down the part begins to power up the part enters full power-down figure 19. entering full power-down mode 1 16 10 116 invalid data valid data cs sclk d out a d out b the part begins to power up the part is fully powered up t power up figure 20. exiting full power-down mode then, to place the AD7866 in normal mode, a dummy cycle (1 s to 4 s approximately) should be initiated. if the first valid conversion is performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first sclk edge applied after the falling edge of cs . however when the adc initially powers up after supplies are applied, the track- and-hold will already be in track. this means that (assuming one has the facility to monitor the adc supply current and thus determine which mode the AD7866 is in) if the adc powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle re quired to place the track-and-hold into track. if no current monitoring facility is available, the relevant dummy cycle(s) should be performed to ensure the part is in the re quired mode.
rev. a ?8 AD7866 power vs. throughput rate when the AD7866 is in partial power-down mode and not converting, the average power consumption of the adc de creases at lower throughput rates. figure 21 shows that as the through- put rate is reduced, the part remains in its partial power-down state longer, and the average power consumption over time drops accordingly. throughput ?ksps 0.01 0 power ?mw 50 100 v dd = 5v sclk = 20mhz 150 200 250 300 350 0.1 1 10 100 v dd = 3v sclk = 20mhz figure 21. power vs. throughput for partial power-down for example, if the AD7866 is operated in a continuous sam pling mode with a throughput rate of 100 ksps and an sclk of 20 mhz (v dd = 5 v), and the device is placed in partial p ower- down mode between conversions, the power consumption is calculated as follows. the maximum power dissipation during normal operation is 24 mw (v dd = 5 v). if the power-up time allowed from partial power-down is one dummy cycle, i.e., 1 s, (assuming use of an external reference) and the remaining con version time is another cycle, i.e., 1 s, then the AD7866 can be said to dissipate 24 mw for 2 s during each conversion cycle. for the remainder of the conversion cycle, 8 s, the part remains in partial power-down mode. the AD7866 can be said to dissipate 2.8 mw for the remaining 8 s of the conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each cycle is (2/10) (24 mw) + (8/10) (2.8 mw) = 7.04 mw. if v dd = 3 v, sclk = 20 mhz, and the device is again in partial power-down mode between conversions, the power dissipated during normal operation is 11.4 mw. the AD7866 can be said to dissipate 11.4 mw for 2 s during each conversion cycle and 1.68 mw for the remaining 8 s when the part is in partial power-down. with a throughput rate of 100 ksps, the average power dissipated during each conversion cycle is (2/10) (11.4 mw) + (8/10) (1.68 mw) = 3.624 mw. figure 21 shows the maximum power versus throughput rate when using the partial power-down mode between conversions with both 5 v and 3 v supplies for the AD7866. serial interface figure 22 shows the detailed timing diagram for serial interfacing to the AD7866. the serial clock provides the conversion clock and controls the transfer of information from the AD7866 dur ing conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state; the analog input is sampled at this point. the conversion is also initiated at this point and requires 16 sclk cycles to complete. once 13 sclk falling edges have elapsed, the track-and-hold will go back into track on the next sclk rising edge, as shown in figure 22 at point b. on the rising edge of cs , the conversion will be terminated and d out a an d d out b will go back into three-state. if cs is not brought high but is instead held low for a further 16 sclk cycles on d out a, the data from conversion b will be output on cs sclk d out a d out b t 2 12345 13141516 t 3 t 4 t 7 t 5 t 8 t quiet 0 range a0 a/b db11 db2 db1 db0 three- state 1 leading zero 3 status bits db10 three- state t 6 b figure 22. serial interface timing diagram cs sclk d out a t 2 t 4 t 7 t 5 0 range db11 a a0/ a0 zero db1 a db0 a zero range a0/ a0 one db11 b db1 b db0 b three- state t 6 t 9 1 leading zero 3 status bits 1 leading zero 3 status bits three- state t 3 1 2 3 4 5 14 15 16 17 32 figure 23. reading data from both adcs on one d out line
rev. a AD7866 ?9 d out a. likewise, if cs is held low for a further 16 sclk cycles on d out b, the data from conversion a will be output on d out b. this is illustrated in figure 23 where the case for d out a is shown. note that in this case, the d out line in use will go back into three-state on the 32nd sclk rising edge or the rising edge of cs , whichever occurs first. sixteen serial clock cycles are required to perform the conver sion process and to access data from one conversion on either data line of the AD7866. cs going low provides the leading zero to be read in by the microcontroller or dsp. the remaining data is then clocked out by subsequent sclk falling edges, beginning with the first of three data status bits. thus the first falling clock edge on the serial clock has the leading zero provided and also clocks out the first of three status bits. the final bit in the data transfer is valid on the sixteenth falling edge, having being clocked out on the previous (fifteenth) falling edge. in applications with a slower sclk, it is possible to read in data on each sclk rising edge, i.e., the first rising edge of sclk after the cs falling edge would have the leading zero provided and the fifteenth rising sclk edge would have db0 provided. the three status bits that follow the leading zero provide infor- mation with respect to the conversion result that follows them on the d out line in use. table iii shows how these identifica- tion bits can be interpreted. microprocessor interfacing the serial interface on the AD7866 allows the parts to be directly connected to a range of many different microprocessors. this section explains how to interface the AD7866 with some of the more common microcontroller and dsp serial interface protocols. AD7866 to adsp-218x the adsp-218x family of dsps is directly interfaced to the AD7866 without any glue logic required. the v drive pin of the AD7866 takes the same supply voltage as that of the adsp- 218x. this allows the adc to operate at a higher supply voltage than the serial interface, i.e., adsp-218x, if necessary. this example shows both d out a and d out b of the AD7866 connected to both serial ports of the adsp-218x. table iii. status bit description bit bit name comment 15 zero leading zero. this bit will always be a zero output. 14 range the polarity of this bit reflects the analog input range that has been selected with the range pin. if it is a 0, it means that in the previous transfer upon the falling edge of the cs , the range pin was at a logic low, providing an analog input range from 0 v to v ref for this conversion. if it is a 1, it means that in the previous transfer upon the falling edge of cs , the range pin was at a logic high, resulting in an analog input range of 2 v ref selected for this conversion. see analog input section. 13 a0 this bit indicates on which channel the conversion is being performed, channel 1 or channel 2 of the adc in question. if this bit is a 0, the conversion result will be from channel 1 of the adc; if it is a 1, the result will be from channel 2 of the adc in question. 12 a/b this bit indicates from which adc the conversion result comes. if this bit is a 0, the result is from adc a; if it is a 1, the result is from adc b. this is especially useful if only one serial port is available for use and one d out line is used, as shown in figure 23. the sport0 control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data-words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0 itfs = 1 the sport1 control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data-words isclk = 0, external serial clock tfsr = rfsr = 1, frame every word irfs = 0 itfs = 1 to implement the power-down modes on the AD7866, slen should be set to 1001 to issue an 8-bit sclk burst. the con nection diagram is shown in figure 24. the adsp-218x has the tfs0 and rfs0 of the sport0 and the rfs1 of sport1 tied together, with tfs0 set as an output and both rfs0 and rfs1 set as inputs. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to cs and, as with all signal processing applications, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc and under certain condi tions, equidistant sampling may not be achieved. the timer and other registers are loaded with a value that will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and there- fore the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (i.e., ax0 = tx0), the state of the sclk is checked. the dsp will wait until the sclk has gone high, low, and high before transmission will start. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data may be transmitted or it may wait until the next clock edge.
rev. a ?0 AD7866 for example, if the adsp-2189 had a 20 mhz crystal such that it had a master clock frequency of 40 mhz, then the master cycle time would be 25 ns. if the sclkdiv register is loaded with the value 3, an sclk of 5 mhz is obtained and eight master clock periods will elapse for every 1 sclk period. depending on the throughput rate selected, if the timer register were loaded with the value, 803, (803 + 1 = 804), for example, 100.5 sclks would occur between interrupts and subsequently between transmit instructions. this situation would result in nonequidistant sampling as the transmit instruction is occurring on an sclk edge. if the number of sclks between interrupts were a whole integer figure of n, equidistant sampling would be implemented by the dsp. AD7866 * v drive d out a d out b cs sclk adsp-218x * dr0 dr1 tfs0 sclk0 rfs0 rsf1 sclk1 * additional pins omitted for clarity v dd figure 24. interfacing the AD7866 to the adsp-218x AD7866 * v drive d out a d out b cs sclk tms320c541 * dr0 dr1 clkx0 clkr0 clkx1 clkr1 * additional pins omitted for clarity v dd fsx0 fsr0 fsr1 figure 25. interfacing the AD7866 to the tms320c541 AD7866 to tms320c541 the serial interface on the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7866. the cs input allows easy interfacing between the tms320c541 and the AD7866 with no glue logic required. the serial ports of th e tms320c541 are set up to operate in burst mode with internal clkx (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control (spc) registers must have the following setup: spc0: fo = 0, fsm = 1, mcm = 1 and txm = 1 spc1: fo = 0, fsm = 1, mcm = 0 and txm = 0 the format bit, fo, may be set to 1 to set the word length to eight bits, in order to implement the power-down modes on the AD7866. the connection diagram is shown in figure 25. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 will provide equidistant sampling. the v drive pin of the AD7866 takes the same supply voltage as that of the tms320c541. this allows the adc to operate at a higher voltage than the serial interface, i.e., tms320c541, if necessary. AD7866 to dsp-563xx the connection diagram in figure 26 shows how the AD7866 can be connected to the essi (synchronous serial interface) of the dsp-563xx family of dsps from motorola. each essi (there are two on-board) is operated in synchronous mode (b it syn = 1 in crb register) with internally generated word length frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in crb). normal operation of the essi is selected by making mod = 0 in the crb. set the word length to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. to implement the power-down modes on the AD7866, the word length can be changed to eight bits by setting bits wl1 = 0 and wl0 = 0 in cra. the fsp bit in the crb should be set to 1 to make the frame sync negative. it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the dsp- 563xx provide equidistant sampling. in the example shown in figure 26, the serial clock is taken from the essi0, so the sck0 pin must be set as an output, sckd = 1, while the sck1 pin is set up as an input, sckd = 0. the frame sync signal is taken from sc02 on essi0, so scd2 = 1, w hile on essi1, scd2 = 0, so sc12 is configured as an input. the v drive pin of the AD7866 takes the same supply voltage as that of the dsp-563xx. this allows the adc to operate at a higher voltage than the serial interface, i.e., dsp-563xx, if necessary. AD7866 * v drive d out a d out b cs sclk dsp-563xx * sc02 sc12 sck0 srd0 srd1 sck1 * additional pins omitted for clarity v dd figure 26. interfacing to the dsp-563xx application hints grounding and layout the analog and digital supplies to the AD7866 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the AD7866 has very good immunity to noise on the power supplies as can be shown by the psrr vs. supply ripple frequency plots, tpc 3a to tpc 4b. how ever, care should be taken with regard to grounding and layout. the printed circuit board that houses the AD7866 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum
rev. a AD7866 ?1 etch technique is generally best for ground planes because it gives the best shielding. both agnd pins of the AD7866 should be sunk in the agnd plane. digital and analog ground planes should be joined at only one place. if the AD7866 is in a system where mu ltiple devices require an agnd to dgnd connec- ti on, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7866. avoid running digital lines under the device since these will couple noise onto the die. the analog ground plane should be all owe d to run under the AD7866 to avoid noise coupling. the power supply lines to the AD7866 should use the largest trace pos sible to provide low impedance paths and to reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radi ating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. for this technique, the component side of the board is dedicated to ground planes while signals are placed on the sol der side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f capaci tors to agnd. all digital supplies should have at least a 0.1 f disk ceramic capacitor to dgnd. v drive should have a 0.1 f ce ramic capacitor to dgnd. to achieve the best results from these decoupling components, place them as close as possible to the device, ideally right up against it. the 0.1 f capacitors should be common ceramic or surface-mount types, which have low effective series resistance (esr) and effective series induc tance (esi), and provide a low impedance path to ground at high frequencies for handling transient currents due to internal logic switching. figure 27 shows the recommended supply d ecoupling scheme. for information on the decoupling requirements of each reference configuration, see the reference configuration op tions section. agnd dgnd AD7866 dv dd av dd 0.1 f10 f agnd 0.1 f 10 f v drive 0.1 f figure 27. recommended supply decoupling scheme evaluating the AD7866 performance the recommended layout for the AD7866 is outlined in the evaluation board for the AD7866. the evaluation board package includes a fully assembled and tested evaluation board, documen- tation, and software for controlling the board from the pc via the eval-controller board. the eval-controller board can be used in conjunction with the AD7866 e valua tion board, as well as many other analog devices evaluation boards ending in the cb desig- nator, to demonstrate/evaluate the ac and dc performance of the AD7866. the software allows the user to perform ac (fast fourier trans form) and dc (histogram of codes) tests on the AD7866.
rev. a ?2 AD7866 outline dimensions 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10
rev. a AD7866 ?3 revision history location page 2/03?ata sheet changed from rev. 0 to rev. a. addition to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 addition to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 added text to analog input ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 changes to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 changes to power vs. throughput rate section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 replaced figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
c02672??/03(a) printed in u.s.a. ?4

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